1. Field of the Invention
The present invention relates to an emitter coupled logic (hereinafter referred to as "ECL") output circuit.
2. Description of the Related Art
An ECL circuit has been conventionally known as an integrated circuit which has a function of an extra high speed logic operation, and has been widely used as an output device particularly for a computer, a communication appliance, etc.
FIG. 1 shows such a conventional ECL output circuit. Here, if an input signal having an "H" level, which is higher than a reference poten ial at a reference terminal 2, is applied to an input terminal 1, a transistor Q.sub.1 is turned on, but a transistor Q.sub.2 is turned off, so that no current flows through a load resistor R.sub.2. Accordingly, assuming that a potential of a higher potential supply terminal 5 is 0 V, and that a base-emitter forward voltage V.sub.BEQ3 of a transistor Q.sub.3 is 0.8 V, then a potential V.sub.3 of an output terminal 3 becomes as follows. ##EQU1## The potential V.sub.3 shows an "H" level.
Next, when an input signal of an "L" level, which is lower than the reference potential at the reference terminal 2, is applied to the input terminal 1, the transistor Q.sub.1 is turned off, while the transistor Q.sub.2 is turned on. Accordingly, assuming that a current I.sub.4 of a constant-current source 4 is 0.2 mA, and that the load resistor R.sub.2 is 3 k.OMEGA., then the potential V.sub.3 at the output terminal 3 becomes as follows. ##EQU2## Thus, the potential V.sub.3 shows an "L" level.
Generally, the reference potential at the reference potential 2 is set to -1.1 V in the circuit shown in FIG. 1.
Here, if a potential V.sub.6 at a lower potential supply terminal 6 is equal to -4.5 V, a power consumption P.sub.CS of the current-switching type logic circuit becomes as follows. ##EQU3##
Further, in the case where a resistance R.sub.4 is selected to be 15.5 k.OMEGA., a power comsumption P.sub.EF of the emitter follower circuit, that is, the ECL output circuit is expressed as follows.
When the output terminal 3 is in the "H" level: EQU I.sub.R4(H) =(V.sub.OH -V.sub.6)/R.sub.4 =0.24 (mA) (4) EQU P.sub.EF(H) =.vertline.V.sub.6 .vertline..multidot.I.sub.R4(H) =1.08 (mW)(5)
When the output 3 is in the "L" level: EQU I.sub.R4(L) =(V.sub.OL -V.sub.6)/R.sub.4 =0.20 (mA) (6) EQU P.sub.EF(L) =.vertline.V.sub.6 .vertline..multidot.I.sub.R4(L) =0.9 (mW)(7)
Further, in FIG. 1, C.sub.L represents a load capacitance at the output terminal 3.
An integrated circuit having ECLs as basic circuits is constituted by a number of such circuits as shown in FIG. 1. Accordingly, as circuit integration is progressed, power consumption increases. It is, however, impossible to increase the power consumption limitlessly in view of the limitation in system power consumption, in junction temperature of the device, etc. Accordingly, it is necessary to reduce the power consumption in the ECL basic circuit shown in FIG. 1.
The reduction of power consumption means to decrease the current I.sub.4 in the above equation (3) and the currents I.sub.R4(H) and I.sub.R4(L) in the equations (5) and (7). Accordingly, the reduction of power consumption deteriorates the high-seed operation which is the largest advantage of the ECL circuit. Specifically, if the current I.sub.R4(L) is made small, that is, the resistance value of the resistor R.sub.4 is made high, the operation speed remarkably deteriorates in the falling change period of the output signal at the output terminal 3.
Assuming that the value of a load capacitance C.sub.L is 1 pF, the respective falling change periods of time of the output become as follows in the respective cases of R.sub.4 =15.5 k.OMEGA. and R.sub.4 =31 k.OMEGA.. ##EQU4##
Further, as apparent from the above equations (5) and (7), the power consumption R.sub.EF(H) in the "H" level period at the output terminal 3 is larger than the power consumption P.sub.EF(L) in the "L" level period at the same terminal output 3. It is better for the power consumption P.sub.EF(H) to be smaller in the high-speed operation of the ECL circuit. The conventional circuit as shown in FIG. 1 had the disadvantage that the power consumption was wasted because the power consumption P.sub.EF(H) was large.